set_property LOC K17 [get_ports clk]
set_property LOC E17 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]

set_property LOC M15 [get_ports {gpio_o[0]}]
set_property LOC G14 [get_ports {gpio_o[1]}]
set_property LOC M17 [get_ports {gpio_o[2]}]
set_property LOC G15 [get_ports {gpio_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_o[1]}]

set_property LOC T19 [get_ports uart_rx]
set_property PULLUP true [get_ports uart_rx]
set_property IOSTANDARD LVCMOS33 [get_ports uart_rx]
set_property LOC T14 [get_ports uart_tx]
set_property PULLUP true [get_ports uart_tx]
set_property IOSTANDARD LVCMOS33 [get_ports uart_tx]

create_clock -period 20.000 -name CLK -waveform {0.000 10.000} -add [get_ports clk]

set_input_delay -clock [get_clocks CLK] -min -add_delay 1.000 [get_ports rst_n]
set_input_delay -clock [get_clocks CLK] -max -add_delay 2.000 [get_ports rst_n]
set_input_delay -clock [get_clocks CLK] -min -add_delay 1.000 [get_ports uart_rx]
set_input_delay -clock [get_clocks CLK] -max -add_delay 2.000 [get_ports uart_rx]
set_output_delay -clock [get_clocks CLK] -min -add_delay 0.000 [get_ports {gpio_o[*]}]
set_output_delay -clock [get_clocks CLK] -max -add_delay 2.000 [get_ports {gpio_o[*]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 0.000 [get_ports uart_tx]
set_output_delay -clock [get_clocks CLK] -max -add_delay 2.000 [get_ports uart_tx]

